1. Field of the Invention
The present invention relates to a semiconductor device and to a test method of the semiconductor device.
2. Description of the Related Art
Patent Document 1 (JP-A-2005-158221) discloses a typical form of a phase-change memory (PRAM: phase-change random access memory) device that is a nonvolatile memory device that stores data by using phase-change memory elements that are formed of a phase-change material in which resistance is changed by phase transitions.
The operation of writing data (hereinbelow referred to as a write operation) to a phase-change memory device includes a set operation of writing data by changing phase-change material from an amorphous state to a crystalline state and a reset operation of writing data by changing the phase-change material from a crystalline state to an amorphous state.
In a write operation, a pulse current is applied to the phase-change material, and this operation is characterized in that the time interval of the application of this pulse current is shorter at the time of the reset operation than at the time of the set operation and the amount of current of this pulse current is greater at the time of the reset operation than at the time of the set operation (see FIG. 12 and FIG. 13 of Patent Document 1).
In the operation control of a phase-change memory device having the above-described characteristics, the timing of a write operation is determined according to the set operation, which takes more time to write data, to enable the writing of data in a set operation as well as in a reset operation.
In addition, in an operation test of a typical semiconductor device that is equipped with a memory cell, a test pattern signal is written to the memory cell, following which the test pattern signal is read from the memory cell. The test pattern signal that was read is then compared with the test pattern signal that was written.
When the semiconductor device is equipped with a plurality of memory banks in the above-described operation test, there is a method that can shorten the time relating to the operation test by simultaneously writing the test pattern signal to each memory bank.
However, in the case of a phase-change memory device, the amount of current relating to the write operation of a phase-change memory device is relatively great and the amount of current therefore becomes excessive when the test pattern signal is simultaneously written to each memory bank. As a result, simultaneously writing the test pattern signal to each memory bank is problematic.
Accordingly, the write operation must be carried out separately to each memory bank in a phase-change memory device, as shown in FIG. 1. However, the timing of the write operation is determined according to the set operation, which takes more time to write data, and when the write operation is carried out separately for each memory bank, the problems arise that the time relating to the operation test becomes exceedingly long and the costs relating to the operation test become prohibitive.